Login / Signup
Design and Verification for Hierarchical Power Efficiency System (HPES) Design Techniques Using Low Power CMOS Digital Logic.
Taikyeong T. Jeong
Jaemyoung Lee
Published in:
International Conference on Computational Science (1) (2006)
Keyphrases
</>
low power
power consumption
single chip
low cost
design process
low power consumption
high speed
power dissipation
circuit design
logic circuits
mixed signal
cmos image sensor
chip design
power reduction
nm technology