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A Reference-Free Capacitive-Discharging Oscillator Architecture Consuming 44.4 pW/75.6 nW at 2.8 Hz/6.4 kHz.
Hui Wang
Patrick P. Mercier
Published in:
IEEE J. Solid State Circuits (2016)
Keyphrases
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error prone
high speed
real time
distributed architecture
hardware architecture
neural network
case study
data structure
software architecture
differential equations
hardware implementation
loosely coupled
sampling rate
design considerations
layered architecture