Block-Parallel Systolic-Array Architecture for 2-D NTT-based Fragile Watermark Embedding.
Arjuna MadanayakeRenato J. CintraVassil S. DimitrovLeonard T. BrutonPublished in: CoRR (2022)
Keyphrases
- systolic array
- parallel architecture
- data flow
- watermark embedding
- parallel processing
- spread spectrum
- shared memory
- watermarking scheme
- distributed memory
- watermarking algorithm
- dct coefficients
- hardware implementation
- copyright protection
- image watermarking
- parallel implementation
- jpeg compression
- pattern recognition
- visual quality
- computer simulation