A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes.
Jeffrey S. ReeveKosala AmarasinghePublished in: ICC (2004)
Keyphrases
- fpga implementation
- hardware implementation
- field programmable gate array
- block codes
- decoding algorithm
- error correction
- image processing algorithms
- parallel computing
- parallel processing
- image processing
- massively parallel
- shared memory
- hidden markov models
- transfer function
- data processing
- signal processing
- error control
- computer vision