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Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology.

Qing XieYanzhi WangShuang ChenMassoud Pedram
Published in: ICCD (2014)
Keyphrases
  • joint optimization
  • metal oxide semiconductor
  • high speed
  • integrated circuit
  • neural network
  • computational complexity
  • nm technology
  • silicon on insulator
  • case study
  • computer systems
  • eeg signals