Low-Power Way-Predicting Cache Using Valid-Bit Pre-Decision for Parallel Architectures.
Hsin-Chuan ChenJen-Shiun ChiangPublished in: AINA (2005)
Keyphrases
- low power
- parallel architectures
- power consumption
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- high speed
- parallel processing
- massively parallel
- single chip
- low power consumption
- parallel computing
- computing systems
- efficient implementation
- logic circuits
- nm technology
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- power dissipation
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- query processing
- signal processing