FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder.
Man GuoM. Omair AhmadM. N. Shanmukha SwamyChunyan WangPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2005)
Keyphrases
- low power
- single chip
- low power consumption
- systolic array
- gate array
- vlsi architecture
- high speed
- low cost
- power consumption
- cmos technology
- power reduction
- digital signal processing
- logic circuits
- ultra low power
- power dissipation
- real time
- reconfigurable architecture
- low complexity
- fpga implementation
- parallel architecture
- design methodology
- hardware architecture
- power saving
- data flow
- mixed signal
- signal processor
- efficient implementation
- vlsi implementation
- vlsi circuits
- video decoder
- signal processing
- hidden markov models
- pattern recognition