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An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance.

Chung-Cheng ChouZheng-Jun LinPei-Ling TsengChih-Feng LiChih-Yang ChangWei-Chi ChenYu-Der ChihTsung-Yung Jonathan Chang
Published in: ISSCC (2018)
Keyphrases
  • low voltage
  • simulated annealing
  • power line
  • design considerations
  • read write
  • pattern recognition
  • multimedia
  • response time
  • context aware
  • power management