Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits.

Vasanth Kakani Foster F. Dai Richard C. Jaeger

Published in: ISCAS (2) (2004)

Keyphrases

low power
high speed
logic circuits
low cost
power consumption
power dissipation
wireless transmission
single chip
gate array
real time
high power
vlsi architecture
low power consumption
wireless sensor networks
efficient implementation
functional decomposition