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Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme.
Mingqiang Huang
Yucen Liu
Sixiao Huang
Kai Li
Qiuping Wu
Hao Yu
Published in:
FPGA (2023)
Keyphrases
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systolic array
data flow
parallel architecture
neural network
digital signal processor
cellular neural networks
protection scheme
real time
image segmentation
motion estimation
signal processing
parallel implementation
integer arithmetic