A VLSI Layout for a Pipelined Dadda Multiplier
Peter R. CappelloKenneth SteiglitzPublished in: ACM Trans. Comput. Syst. (1983)
Keyphrases
- data flow
- signal processing
- vlsi circuits
- vlsi design
- floating point
- high speed
- neural network
- hardware implementation
- database systems
- multiscale
- linear programming
- single chip
- layout design
- multi agent
- feature selection
- information systems
- genetic algorithm
- type ii
- data mining
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- linear array
- data sets