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Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example.
Radu Zlatanovici
Sean Kao
Borivoje Nikolic
Published in:
IEEE J. Solid State Circuits (2009)
Keyphrases
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power dissipation
low power
optimal design
nm technology
cmos technology
high speed
optimization algorithm
circuit design
design space
analog to digital converter
evolutionary algorithm
optimum design
image processing algorithms
energy minimization
video coding
pattern matching
design process