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Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA.

Roberto Ramírez MarínAndrés David García GarcíaLuis Fernando González PérezJavier Eduardo González Villarruel
Published in: CONIELECOMP (2005)
Keyphrases
  • hardware architecture
  • hardware implementation
  • single pass
  • computational complexity
  • hardware architectures
  • real time
  • associative memory