High-Resolution Delay Testing of Interconnect Paths in Field-Programmable Gate Arrays.
Jack R. SmithTian XiaPublished in: IEEE Trans. Instrum. Meas. (2009)
Keyphrases
- field programmable gate array
- high resolution
- hardware software co design
- digital signal processing
- power dissipation
- clock frequency
- low resolution
- hardware implementation
- high speed
- embedded systems
- fpga technology
- programmable logic
- hardware and software
- hardware architecture
- power consumption
- computing systems
- image processing
- hardware design
- super resolution
- parallel architectures
- hardware software
- image processing algorithms
- massively parallel
- host computer
- hw sw
- scheduling problem
- real time
- software implementation
- parallel computing
- efficient implementation
- reconfigurable hardware
- parallel programming
- general purpose processors
- computer systems