Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array.
John A. KalomirosJohn N. LygourasPublished in: IET Comput. Digit. Tech. (2008)
Keyphrases
- hardware implementation
- field programmable gate array
- fpga device
- general purpose processors
- parallel architecture
- xilinx virtex
- memory management
- signal processing
- high end
- parallel architectures
- hardware architecture
- fpga implementation
- software implementation
- efficient implementation
- image processing algorithms
- processing elements
- hardware design
- programmable logic
- fpga technology
- dedicated hardware
- stereo matching
- computer vision
- parallel computing
- embedded systems
- hardware software
- clock frequency
- image processing
- pipelined architecture
- depth map
- high speed
- low cost
- general purpose
- reconfigurable hardware
- feature extraction
- information systems
- machine learning
- application specific integrated circuits