Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.
Arindam MallikDebjit SinhaPrithviraj BanerjeeHai ZhouPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
- gate array
- low power
- single chip
- power consumption
- low cost
- logic circuits
- high speed
- cmos image sensor
- low power consumption
- vlsi architecture
- digital signal processing
- mixed signal
- power reduction
- cmos technology
- design methodology
- application specific
- signal processor
- real time
- hardware architecture
- image sensor
- resource allocation
- nm technology
- analog to digital converter
- general purpose