A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer.

Hai Huang Ling Du Yun Chiu

Published in: A-SSCC (2015)

Keyphrases

analog to digital converter
high speed
post processing
low cost
cmos technology
electro optic
nm technology
random access memory
image sensor
sar images
circuit design
synthetic aperture radar
knowledge transfer
real time
power consumption
image reconstruction
parameter estimation
video sequences
multiscale