VLSI Architecture of High Speed SAD for High Efficiency Video Coding (HEVC) Encoder.
Amit Mahesh JoshiMohammad Samar AnsariChitrakant SahuPublished in: ISCAS (2018)
Keyphrases
- high efficiency video coding
- vlsi architecture
- high speed
- video coding
- low power
- motion vectors
- bit rate
- rate distortion
- mode decision
- multiview video coding
- low complexity
- video codec
- motion estimation
- coding method
- macroblock
- motion compensation
- video compression
- real time
- motion compensated
- rate control
- video quality
- computational complexity
- subband
- visual quality
- coding efficiency
- distributed video coding
- image quality
- video sequences
- bitstream
- block size
- high definition
- block matching
- bit allocation
- prediction error
- reference frame
- inter frame
- multiview video
- vlsi implementation
- low cost
- low bit rate
- frame rate
- wyner ziv
- intra prediction
- error concealment
- compression efficiency
- video coding standard
- error resilience
- temporal correlation
- inter view
- power consumption
- video transmission
- stereoscopic video
- video data
- image sequences
- random access
- video conferencing