Formal Verification of GCSE in the Scheduling of High-level Synthesis: Work-in-Progress.
Jian HuYongyang HuLong YuWentao WangHaitao YangYun KangJie ChengPublished in: CODES+ISSS (2020)
Keyphrases
- formal verification
- high level synthesis
- model checking
- model checker
- scheduling algorithm
- symbolic model checking
- bounded model checking
- automated verification
- parallel architecture
- program slicing
- scheduling problem
- design space exploration
- parallel machines
- image processing
- temporal logic
- shared memory
- pairwise
- expert systems
- search algorithm
- image segmentation
- case study
- information systems