Field programmable gate array-based acceleration of shortest-path computation.
George Rosario JagadeeshThambipillai SrikanthanC. M. LimPublished in: IET Comput. Digit. Tech. (2011)
Keyphrases
- shortest path
- field programmable gate array
- pipelined architecture
- hardware implementation
- shortest path problem
- road network
- shortest path algorithm
- path length
- hardware architecture
- embedded systems
- image processing algorithms
- fpga device
- programmable logic
- weighted graph
- travel time
- routing algorithm
- path selection
- parallel computing
- optimal path
- digital signal processors
- fpga technology
- edge weights
- betweenness centrality
- real time
- massively parallel
- data management
- information systems