Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation.
Omayma MatoussiFrédéric PétrotPublished in: DATE (2017)
Keyphrases
- memory hierarchy
- cache misses
- learning disabled students
- level parallelism
- multimedia
- discrete event simulation
- secondary storage
- main memory
- computing power
- computer architecture
- memory access
- monte carlo simulation
- prefetching
- instructional design
- cooperative learning
- replacement policy
- instruction set
- simulation model
- query processing
- neural network