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A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.

Massimo RoviniGiuseppe GentileFrancesco RossiLuca Fanucci
Published in: VLSI-SoC (2007)
Keyphrases
  • ldpc codes
  • decoding algorithm
  • error correction
  • low density parity check
  • message passing
  • channel coding
  • rate allocation
  • image transmission
  • source coding
  • physical layer
  • end to end
  • noise model