1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18µm CMOS.
Pyung-Su HanWoo-Young ChoiPublished in: ISCAS (2006)
Keyphrases
- bit rate
- high speed
- rate distortion
- visual quality
- low bit rate
- image quality
- video coding
- rate control
- subband
- inter frame
- rate distortion optimization
- bitstream
- power consumption
- coding efficiency
- coding method
- video quality
- mode decision
- picture quality
- rate control scheme
- prediction error
- macroblock
- circuit design
- bit allocation
- low power
- motion vectors
- computational complexity
- frame rate
- rate control algorithm
- high quality
- power dissipation