Design of Low Power SAR ADC Using Clock Retiming.
Jalaja SVijaya Prakash A. MPublished in: ISVLSI (2018)
Keyphrases
- low power
- power consumption
- single chip
- high speed
- low power consumption
- low cost
- gate array
- vlsi architecture
- cmos technology
- digital signal processing
- logic circuits
- power reduction
- vlsi circuits
- power dissipation
- wireless transmission
- analog to digital converter
- high power
- mixed signal
- cmos image sensor
- image sensor