Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs.

Fumiya Kono Naohito Nakasato Maho Nakata

Published in: FCCM (2023)

Keyphrases

floating point
matrix multiplication
message passing
distributed memory
fixed point
square root
matrix factorization
instruction set
floating point unit
sparse matrices
hardware implementation
interval arithmetic
floating point arithmetic
three dimensional
special case