Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs.

Published in: CDES (2006)

Keyphrases

square root
floating point
fixed point
field programmable gate array
instruction set
kalman filtering
embedded systems
hardware implementation
euclidean space
floating point arithmetic
image processing
pairwise
nearest neighbor
sufficient conditions