Fault tolerant design for low power hierarchical search motion estimation algorithms.
Charvi DhootVincent John MooneyShubhajit Roy ChowdhuryLap-Pui ChauPublished in: VLSI-SoC (2011)
Keyphrases
- fault tolerant
- low power
- digital signal processing
- motion estimation
- high speed
- single chip
- power consumption
- fault tolerance
- low cost
- logic circuits
- motion estimation algorithm
- vlsi architecture
- low power consumption
- load balancing
- distributed systems
- power dissipation
- video sequences
- design process
- image sequences
- image processing algorithms
- cmos technology
- safety critical
- sensor networks
- computational complexity
- vlsi circuits
- nm technology