A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths.
Chuliang GuoLi ZhangXian ZhouGrace Li ZhangBing LiWeikang QianXunzhao YinCheng ZhuoPublished in: ACM J. Emerg. Technol. Comput. Syst. (2021)
Keyphrases
- hardware implementation
- low cost
- floating point
- bit parallel
- magnetic tape
- field programmable gate array
- data mining
- efficient implementation
- systolic array
- xilinx virtex
- case study
- fine grain
- bit vectors
- interior point methods
- reconfigurable architecture
- information retrieval
- bit vector
- general purpose
- image processing algorithms
- multi objective
- embedded systems
- signal processing