An 8-b 100-MSample/s CMOS pipelined folding ADC.

Myung-Jun Choe Bang-Sup Song Kantilal Bacrania

Published in: IEEE J. Solid State Circuits (2001)

Keyphrases

analog to digital converter
single chip
power consumption
analog vlsi
circuit design
low cost
low power
high speed
cmos image sensor
image sensor
protein folding
linear array
delay insensitive
vlsi circuits
data flow
hardware and software
power supply
sigma delta
energy landscape
nm technology
digital images