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A 60 GHz, 50 mW, 3dB Noise Figure Receiver Frontend Using UMC 40 nm CMOS technology.
Pritesh Kumar Yadav
Prashant Kumar
Ankita Verma
Sunanda Ambulker
Prasanna Kumar Misra
Published in:
iSES (2020)
Keyphrases
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cmos technology
power consumption
low power
spl times
power dissipation
high speed
low voltage
parallel processing
clock frequency
power management
signal to noise ratio
mixed signal
low cost
silicon on insulator
image sensor
digital signal processing
frequency band
computer vision