VLSI configurable delay commutator for a pipeline split radix FFT architecture.
Jesús GarcíaJuan A. MichellAngel M. BurónPublished in: IEEE Trans. Signal Process. (1999)
Keyphrases
- fourier transform
- floating point
- pipeline architecture
- signal processing
- data conversion
- real time
- printed circuit
- parallel architecture
- vlsi implementation
- vlsi architecture
- hardware implementation
- power dissipation
- data model
- processor array
- fixed point
- low power
- general purpose
- fast fourier transform
- management system
- metadata