A Highly Efficient QEC Decoder Implemented on FPGA and ASIC.
Kenton M. BarnesTomasz BialasOkan BugdayciEarl T. CampbellNeil I. GillespieKauser JoharRam RajanAdam W. RichardsonLuka SkoricCanberk TopalMark L. TurnerAbbas B. ZiadPublished in: QCE (2023)
Keyphrases
- highly efficient
- hardware implementation
- low complexity
- low cost
- fpga implementation
- hardware architecture
- single chip
- pipelined architecture
- real time
- field programmable gate array
- high speed
- gray code
- low latency
- signal processing
- application specific
- fpga device
- reconfigurable hardware
- fpga hardware
- image processing algorithms
- low power
- motion estimation
- search algorithm
- genetic algorithm