Hardware Flexible Systolic Architecture for Convolution Accelerator in Convolutional Neural Networks.
Paulo Aaron Aguirre-ÁlvarezJavier Díaz-CarmonaMoisés Arredondo-VelázquezPublished in: TSP (2022)
Keyphrases
- convolutional neural networks
- hardware architecture
- real time
- vlsi implementation
- hardware implementation
- vlsi architecture
- field programmable gate array
- software implementation
- image processing
- convolutional network
- pipeline architecture
- low cost
- hardware design
- computing platform
- hardware software
- highly flexible
- instruction set
- hardware architectures
- dedicated hardware
- hardware and software
- fpga technology
- systolic array
- reconfigurable hardware
- parallel implementation
- multithreading
- processing units
- parallel architecture
- central processor
- management system
- heterogeneous computing
- abstraction layer
- embedded systems
- fpga device
- commercial off the shelf
- fir filters