Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.

Payam Heydari Ravindran Mohanavelu

Published in: IEEE Trans. Very Large Scale Integr. Syst. (2004)

Keyphrases

low voltage
cmos technology
design considerations
high speed
low power
power dissipation
case study
power consumption
design process
circuit design
low cost
real time
computer systems
collaborative learning
signal processing
random access memory
power line