A 131.5-137.5 GHz Low-Power Sub-Harmonic Receiver Using a 65-nm CMOS Technology.

Hyunkyu Lee Eunjung Kim Sanggeun Jeon

Published in: IEEE Access (2024)

Keyphrases

cmos technology
low power
high speed
power consumption
clock frequency
low cost
low voltage
mixed signal
single chip
low power consumption
digital signal processing
silicon on insulator
power dissipation
frame rate
real time
image sensor
power management
efficient implementation
power reduction
digital images