Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction Debugging.
Vibarajan ViswanathanJuliet RunhaarDoug ReedJun ZhaoPublished in: MTV (2016)
Keyphrases
- hardware designs
- database
- software tools
- model checking
- formal methods
- query processing
- program understanding
- formal verification
- concurrency control
- user friendly
- source code
- end users
- software components
- distributed databases
- transaction model
- replacement policy
- programs written
- hardware description language
- cache consistency