Model Checking and Co-simulation of a Dynamic Task Dispatcher Circuit Using CADP.
Etienne LantreibecqWendelin SerwePublished in: FMICS (2011)
Keyphrases
- model checking
- temporal logic
- formal verification
- dynamic analysis
- partial order reduction
- model checker
- automated verification
- formal specification
- temporal properties
- computation tree logic
- bounded model checking
- symbolic model checking
- finite state
- timed automata
- finite state machines
- verification method
- pspace complete
- asynchronous circuits
- process algebra
- linear temporal logic
- formal methods
- reachability analysis
- epistemic logic
- deterministic finite automaton
- artificial intelligence
- abstract interpretation
- ordered binary decision diagrams
- alternating time temporal logic