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A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC.
Young-Ju Kim
Hee-Cheol Choi
Si-Wook Yoo
Seung-Hoon Lee
Dae-Young Chung
Kyoung-Ho Moon
Ho-Jin Park
Jae-Whui Kim
Published in:
CICC (2007)
Keyphrases
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low power
power consumption
low cost
single chip
high speed
logic circuits
high power
low power consumption
wireless transmission
vlsi architecture
vlsi circuits
real time
power reduction
cmos technology
digital signal processing
image sensor
embedded systems