Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA.
Eric MatthewsZavier AguilaLesley ShannonPublished in: FCCM (2018)
Keyphrases
- variable length
- parallel execution
- instruction set
- instruction set architecture
- fixed length
- parallel processing
- parallel architectures
- hardware architecture
- processing units
- embedded systems
- application specific
- parallel computing
- n gram
- floating point
- field programmable gate array
- computer architecture
- data partitioning
- shared memory
- processing elements
- real time
- hardware implementation
- bitstream
- cost model
- hardware software
- functional units
- parallel programming
- parallel computers
- human motion
- memory management
- memory access
- machine learning