Hardware-Aware Pruning for FPGA Deep Learning Accelerators.
Jef PlochaetToon GoedeméPublished in: CVPR Workshops (2023)
Keyphrases
- deep learning
- field programmable gate array
- hardware implementation
- single chip
- embedded systems
- hardware architecture
- hardware design
- parallel computing
- unsupervised learning
- image processing algorithms
- computing systems
- unsupervised feature learning
- low cost
- machine learning
- xilinx virtex
- general purpose processors
- mental models
- massively parallel
- weakly supervised
- computing platform
- low power
- signal processing
- learning algorithm
- learning strategies
- high dimensional
- multiscale
- feature selection
- ibm power processor