Sorter Design with Structured Low Power Techniques.
PreethiMohan Govindsa KabadiSudeendra Kumar KK. K. MahapatraPublished in: SN Comput. Sci. (2023)
Keyphrases
- low power
- power consumption
- single chip
- low power consumption
- high speed
- logic circuits
- low cost
- vlsi architecture
- ultra low power
- gate array
- mixed signal
- power dissipation
- digital signal processing
- power reduction
- wireless transmission
- cmos technology
- real time
- high power
- design methodology
- image sensor
- signal processing
- image processing