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Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
Jia Di
Jiann-Shiun Yuan
Ronald F. DeMara
Published in:
Integr. (2006)
Keyphrases
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three dimensional
design process
power consumption
filter design
programmable logic
neural network
software architecture
design methodology
fir filters
linear array