Low power mapping optimization of loops for dual-Vdd CGRAs.

Kaijian Yuan Xingming Zhang

Published in: ASICON (2017)

Keyphrases

low power
power consumption
low cost
high speed
single chip
high power
logic circuits
vlsi architecture
low power consumption
image sensor
digital signal processing
cmos technology
coarse grained
power reduction
vlsi circuits
level parallelism
nm technology