A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization.
Heejae HwangJongsun KimPublished in: ISOCC (2019)
Keyphrases
- low power
- mixed signal
- low cost
- power consumption
- high speed
- vlsi circuits
- single chip
- high power
- low power consumption
- vlsi architecture
- logic circuits
- multi channel
- cmos technology
- channel estimation
- wireless transmission
- decision feedback
- real time
- digital signal processing
- cmos image sensor
- error propagation
- power reduction
- delay insensitive
- signal processing