A Scalable Hardware Implementation of a Best-Effort Scheduler for Multicore Processors.
Daniel GregorekChristof OsewoldAlberto García OrtizPublished in: DSD (2013)
Keyphrases
- hardware implementation
- multicore processors
- efficient implementation
- computing power
- highly parallel
- parallel architectures
- signal processing
- hardware design
- software implementation
- packet scheduling
- dedicated hardware
- fpga implementation
- image processing algorithms
- operating system
- field programmable gate array
- quality of service
- parallel programming
- parallel algorithm
- computing systems
- image processing
- high end
- scheduling algorithm
- computer systems
- fpga technology