An Efficient Reconfigurable SOS Montgomery Multiplier in GF (P) usign FPGA DSP Slices.
Muhammed Nauman QureshiMuhammad Nadeem SialNassar IkramPublished in: SECRYPT (2008)
Keyphrases
- hardware implementation
- fpga implementation
- field programmable gate array
- xilinx virtex
- signal processing
- digital signal
- systolic array
- digital signal processing
- efficient implementation
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- hardware architecture
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- high speed
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- real time image processing
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- parallel computing
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- image compression