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A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation.
Jian-An Wang
Yuan-Yao Zhao
Zheng-Ping Zhang
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2020)
Keyphrases
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buffer size
high speed
cmos technology
genetic algorithm
significant improvement
code length