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RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey.
Yehya Nasser
Jordane Lorandel
Jean-Christophe Prévotet
Maryline Hélard
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2021)
Keyphrases
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integrated circuit
high speed
hardware implementation
hardware architecture
hardware description language
application specific
accurate estimation
single chip
low cost
power consumption
power reduction
general purpose
low power
levels of abstraction
power saving