3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.
Takashi KawamotoTakayasu NorimatsuKenji KogoFumio YukiNorio NakajimaMasatoshi TsugeTatsunori UsugiTomofumi HokariHideki KobaTakemasa KomoriJunya NasuTsuneo KawamataYuichi ItoSeiichi UmaiJun KumazawaHiroaki KurahashiTakashi MutoTakeo YamashitaMasatoshi HasegawaKeiichi HigetaPublished in: ISSCC (2015)