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A pipelined processor suitable for a bus-based parallel architecture.
Behnam S. Arad
Hung-Ru Shih
Published in:
CATA (2001)
Keyphrases
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parallel architecture
parallel processing
hardware implementation
systolic array
shared memory
parallel implementation
high level synthesis
distributed memory
high speed
processing elements
synthetic aperture sonar
image processing
multi agent
cooperative
post processing